Job Title: Junior Formal Verification Engineer
Location: San Jose (Onsite)
Experience Level: 2–3 Years
Full-time: Salary + Benefits / Contractor
Work Status: US Citizen or US Permanent Resident

Key Responsibilities

• Architect and implement formal verification environments using SystemVerilog and Assertions (SVA).
• Create and refine constraints, properties, and cover directives to ensure thorough design verification.
• Apply formal equivalence checking techniques for RTL vs. C-model datapath validation and clock gating logic.
• Debug formal failures and perform root cause analysis in close collaboration with design engineers.
• Drive property-based feature verification for complex GPU subsystems.
• Apply advanced formal convergence techniques such as abstraction, blackboxing, and design reduction.
• Analyze proof quality and optimize verification strategies for deeper coverage.
• Work across disciplines—design, software, architecture—to align verification goals with broader project requirements.
• Document verification plans, convergence metrics, and test reports using JIRA, Confluence, and other project management tools.
• Contribute to the enhancement of internal formal methodology, tools, and best practices.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science with 3+ years of relevant experience
• Master’s or Ph.D. preferred
• Solid understanding of GPU or CPU microarchitecture
• Proficiency in SystemVerilog and SystemVerilog Assertions (SVA)
• Strong experience with formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
• Hands-on experience with datapath formal verification involving C-to-RTL equivalence
• Familiarity with formal proof strategies, including depth analysis and convergence metrics
• Strong Linux development background

Preferred Experience

• Exposure to constrained-random testbench development
• Contributions to the evolution of formal verification flows and infrastructure
• Background in functional safety or formal verification for safety-critical applications

The anticipated annual base salary for this position is between $80,000 to $100,000, which also includes a comprehensive benefits package.

Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement

Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.